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  ? semiconductor components industries, llc, 2011 october, 2011 ? rev. 0 1 publication order number: amis ? 30421/d amis-30421 micro-stepping stepper motor bridge controller introduction the amis ? 30421 is a micro - stepping stepper motor bridge controller for large current range bipolar applications. the chip interfaces via a spi interface with an external controller in order to control 2 external power nmos h ? bridges. it has an on - chip voltage regulator, current sensing, self adapting pwm controller and pre - driver with smart slope control switching allowing the part to be emc compliant with industrial and automotive applications. it uses a proprietary pwm algorithm for reliable current control. the amis ? 30421 contains a current translation table and takes the next micro - step depending on the clock signal on the ?nxt? input pin and the status of the ?dir? (direction) register or input pin. the chip provides a so - called ?speed and load angle? output. this allows the creation of stall detection algorithms and control loops based on load angle to adjust torque and speed. the amis ? 30421 is implemented in a mature technology, enabling fast high voltage analog circuitry and multiple digital functionalities on the same chip. the chip is fully compatible with automotive voltage requirements. the amis ? 30421 is easy to use and ideally suited for large current stepper motor applications in the automotive, industrial, medical and marine environment. with the on ? chip voltage regulator it further reduces the bom for mechatronic stepper applications. key features ? dual h ? bridge pre ? drivers for 2 ? phase stepper motors ? programmable current via spi ? on ? chip current translator ? spi interface ? speed and load angle output ? 8 step modes from full step up to 64 micro ? steps ? current ? sense via two external sense resistors ? pwm current control with automatic selection of fast and slow decay ? low emc pwm with selectable voltage slopes ? full output protection and diagnosis ? thermal warning and shutdown ? compatible with 3.3 v microcontrollers ? integrated 3.3 v regulator to supply external microcontroller ? integrated reset function to reset external microcontroller ? these devices are pb ? free and are rohs compliant* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. see detailed ordering and shipping information in the package dimensions section on p age 40 of this data sheet. ordering information http://onsemi.com qfn44 case 485by marking diagram 144 amis30421 0c421 ? 001 awlyywwg 1 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package
amis ? 30421 http://onsemi.com 2 block diagram temp . sense otp por di clk nxt sla dir band ? gap load angle amis ? 30421 logic & registers chargepump t r a n s l a t o r vbb vdd gnd cpn cpp vcp rsensxp gxbl gxbr gxtl gxtr p w m i ? sense emc comp rsensxn rsensyp gybl gybr gytl gytr p w m i ? sense emc comp rsensyn clr err test + ? + ? osc motxp motxn motyp motyn vregh cs do wd voltage regulator figure 1. block diagram amis ? 30421 pin out amis ? 30421 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 motxp gxtl gxbr motxn gxtr rsensxp rsensxn vdd gnd vregh sla err clr wd clk di do gybl motyp gytl gybr motyn gytr rsensyp rsensyn dir nxt gxbl nc nc gnd vcp cpp cpn vbb gnd nc nc nc cs nc nc test nc figure 2. pin out amis ? 30421
amis ? 30421 http://onsemi.com 3 table 1. pin list and description name pin description type equivalent schematic gxbl 2 gate of external nmos fet of the x bridge bottom left side analog output motxp 3 positive end of phase x ? coil analog i/o gxtl 4 gate of external nmos fet of the x bridge top left side analog output gxbr 5 gate of external nmos fet of the x bridge bottom right side analog output motxn 6 negative end of phase x ? coil analog i/o gxtr 7 gate of external nmos fet of the x bridge top right side analog output rsensxp 8 resistor sense of the x bridge positive pin analog input rsensxn 9 resistor sense of the x bridge negative pin analog input vdd 10 low voltage supply output (needs external decoupling capacitor) supply type 7 gnd 11 ground, heat sink supply vregh 13 high voltage supply output analog output sla 14 speed and load angle output analog output type 6 errb 15 error output digital output type 2 or 4 clr 16 clear input digital input type 1 wdb 17 watchdog and power on reset output digital output type 2 or 4 clk 18 spi clock input digital input type 1 csb 19 spi chip select input digital input type 3 di 20 spi data input digital input type 1 do 21 spi data output digital output type 2 or 4 test 22 test input. to be tied to ground. digital input type 1 nxt 23 next microstep input digital input type 1 dir 24 direction input digital input type 1 rsensyn 25 resistor sense of the y bridge negative pin analog input rsensyp 26 resistor sense of the y bridge positive pin analog input gytr 27 gate of external nmos fet of the y bridge top right side analog output motyn 28 negative end of phase y ? coil analog i/o gybr 29 gate of external nmos fet of the y bridge bottom right side analog output gytl 30 gate of external nmos fet of the y bridge top left side analog output motyp 31 positive end of phase y ? coil analog i/o gybl 32 gate of external nmos fet of the y bridge bottom left side analog output gnd 37 ground, heat sink supply vbb 38 high voltage supply input supply type 8 cpn 39 negative connection of charge pump capacitor analog i/o cpp 40 positive connection of charge pump capacitor analog i/o vcp 41 charge pump filter capacitor analog i/o gnd 42 ground, heat sink supply nc 1, 12, 33, 34, 35, 36, 43, 44 not connected or connect with ground note: output type of wdb ? , errb ? and do ? pin is selectable through spi
amis ? 30421 http://onsemi.com 4 equivalent schematics following figure gives the equivalent schematics of the user relevant inputs and outputs. the diagrams are simplified representations of the circuits used. r pd vdd in r pu vdd in vdd out vdd sla r out vdd vdd vdd out vbb1 vbb type 1: clk, di, nxt, dir, clr, test input type 2: do, wdb, errb open drain output type 3: csb input type 4: do, wdb, errb push pull output type 6: sla analog output type 7: vdd power supply type 8: vbb power supply note: output type of wdb ? , errb ? and do ? pin is selectable through spi figure 3. in ? and output equivalent diagrams
amis ? 30421 http://onsemi.com 5 electrical specification table 2. absolute maximum ratings (notes 1 and 2) symbol parameter min max unit v bb analog dc supply voltage (note 3) ? 0.3 +40 v i load logic supply external load current, normal mode 0 ? 10 ma logic supply external load current, sleep mode 0 ? 1 ma v rsens voltage on pins rsensxp, rsensxn, rsensyp and rsenyn ? 2.0 +2.0 v v lvio voltage on digital i/o pins and sla ? pin ? 0.3 3.6 v v dd + 0.3 i sla load current on sla ? pin 0 ? 40  a t st storage temperature ? 55 +160 c t j junction temperature under bias (note 4) ? 50 +175 c v hbm human body model electrostatic discharge immunity (note 5) ? 1.5 +1.5 kv v hbm human body model electrostatic discharge immunity, high voltage pins (note 6) ? 4 +4 kv v mm machine model electrostatic discharge immunity (note 7) ? 150 +150 v v cdm charge device model electrostatic discharge immunity (note 8) ? 500 +500 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. if more than one value is mentioned, the most stringent applies. 2. convention: currents flowing in the circuit are defined as positive. 3. +36 v < v bb < +40 v limited to 1 day over lifetime 4. circuit functionality not guaranteed. 5. according to jedec jesd22 ? a114c 6. high voltage pins motxx, vbb, gnd; according to jedec jesd22 ? a114c 7. according to jedec eia ? jesd22 ? a115 ? a 8. according to stm5.3.1 ? 1999 recommend operation conditions operating ranges define the limits for functional operation and parametric characteristics of the device. note that the functionality of the chip outside these operating ranges is not guaranteed. operating outside the recommended operating ranges for extended periods of time may affect device reliability. table 3. operating ranges symbol parameter min max unit v bb analog dc supply +6 +30 v v dd logic supply output voltage (normal mode) +3.0 +3.6 v t j junction temperature (note 9) ? 40 +125 c 9. high junction temperature can result in reduced lifetime.
amis ? 30421 http://onsemi.com 6 table 4. dc parameters the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified. convention: currents flowing in the circuit are defined as positive. symbol pin(s) parameter remark/test conditions min typ max unit supply & voltage regulator v bb vbb nominal operating supply range 6 30 v i bb total internal current consumption unloaded outputs, i int included, h ? bridge disabled 20 ma i sleep sleep mode current consumption unloaded outputs, csb = v dd 150  a v dd vdd regulated output voltage ? 10 ma i load 0 ma 3.0 3.3 3.6 v v dd_sleep regulated output voltage in sleep ? 1 ma i load 0 ma 2.1 2.95 3.63 v i int internal load current unloaded outputs 8 ma i load external load current ? 10 ma i ddlim current limitation pin shorted to ground ? 20 ? 80 ma i load_pd output current in sleep ? 1 ma v regh vregh high voltage regulator v bblv  v bb  30 v based on figure 9 h ? bridge disabled 13.25 v  v bblv  15.75 v 8.0 9.5 11.5 v 6 v  v bb < v bblv based on figure 9 h ? bridge disabled 13.25 v  v bblv  15.75 v v bb v power on reset (por) v ddh vdd internal por comparator threshold v dd rising, see figure 4 1.44 1.8 2.53 v v ddl internal por comparator threshold v dd falling, see figure 4 1.16 1.5 1.93 v ddhys internal por comparator hysteresis 0.3 undervoltage v bbuh vbb v bb undervoltage release level v bb rising, see figure 5 5.5 6.5 v v bbul v bb undervoltage trigger level v bb falling, see figure 5 5.3 6.3 v bbuhys v bb undervoltage hysteresis 0.25 overvoltage v bboh vbb v bb overvoltage trigger level v bb rising, see figure 5 30.0 32.0 v v bbol v bb overvoltage release level v bb falling, see figure 5 29.0 31 v bbohys v bb overvoltage hysteresis 1 pre ? driver i on gxtr, gxtl, gxbr, gxbl, gytr, gytl, gybr, gybl gate charge current selectable through spi ? 1.25 ? 33.00 ma i on_tol gate charge current tolerance ? 45 +45 % i off gate discharge current selectable through spi ? 10.5 ? 115.5 ma i off_tol gate discharge current tolerance ? 45 +45 % r sw switch on ? resistance see also figure 10 5 10 25 
amis ? 30421 http://onsemi.com 7 table 4. dc parameters the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified. convention: currents flowing in the circuit are defined as positive. symbol unit max typ min remark/test conditions parameter pin(s) pre ? driver v sens0 rsensxx pwm comparator toggle level 0 78 100 122 mv v sens1 pwm comparator toggle level 1 105.3 135 164.7 mv v sens2 pwm comparator toggle level 2 156 200 244 mv v sens3 pwm comparator toggle level 3 210.6 270 391.4 mv v sens4 pwm comparator toggle level 4 261.3 335 408.7 mv v sens5 pwm comparator toggle level 5 312 400 488 mv v sens6 pwm comparator toggle level 6 390 500 610 mv v sens7 pwm comparator toggle level 7 468 600 732 mv digital inputs v il clk, di, csb, nxt, dir, clr logic low threshold 0 0.3 x v dd v v ih logic high threshold 0.7 x v dd v dd v r pd internal pull down resistor csb excluded, see also figure 3 25 50 75 k  r pu csb internal pull up resistor see also figure 3 25 50 75 k  digital outputs v ol do, errb, wdb logic low output level output set to type 4 (see figure 3) 0.5 v v oh logic high output level v dd ? 0.5 v ol_open logic low level open drain i ol = 8 ma, output set to type 2 (see figure 3) 0.5 speed and load angle output v out sla output voltage range 0.5 v dd ? 0.5 v v off output offset sla ? pin selectable through spi 0.6 1.2 v v off_tol tolerance on sla output offset ? 17 +17 % g sla gain of sla ? pin = v bemf / v sla selectable through spi 0.0625 1 g sla_tol tolerance on sla gain ? 10 +10 % r out output resistance sla ? pin see also figure 3 1 k  i sla_load load current sla ? pin 0 ? 40  a thermal warning & shutdown t 1 trigger level thermal range 1 see figure 22 ? 5 15 35 c t 2 trigger level thermal range 2 see figure 22 55 70 85 c t 3 trigger level thermal range 3 see figure 22 138 150 162 c t tw thermal warning see figure 22 138 150 162 c t tsd thermal shutdown see figure 22 t tw + 20 c charge pump v cp ? v bb vcp chargepump overdrive voltage based on figure 9 3.5 v bb ? 2.5 15.75 v v cpp ? v cpn chargepump pumping voltage 3.5 v bb ? 2.5 15.75 v c pump external pump capacitor see also c 2 figure 9 220 nf c buffer cpp cpn external buffer capacitor see also c 3 figure 9 220 nf
amis ? 30421 http://onsemi.com 8 table 4. dc parameters the dc parameters are given for v bb and temperature in their operating ranges unless otherwise specified. convention: currents flowing in the circuit are defined as positive. symbol unit max typ min remark/test conditions parameter pin(s) package thermal resistance value rth ja thermal resistance junction ? to ? ambient simulated conform jedec jesd ? 51, (2s2p) 30 k/w simulated conform jedec jesd ? 51, (1s0p) 60 k/w rth jp thermal resistance junction ? to ? exposed pad 0.95 k/w table 5. ac parameter the ac parameters are given for v bb and temperature in their operating ranges unless otherwise specified. symbol pin(s) parameter remark/test conditions min typ max unit internal oscillator f osc frequency of internal oscillator 6.4 8 9.6 mhz power ? up t pu por power ? up time c vdd = 200 nf, see figure 4 60  s t por reset duration see figure 4 80 100 120 ms t rf reset filter time see figure 4 1 15  s t dspi spi delay see figure 4 500  s predriver f pwm pwm frequency frequency depends only on internal oscillator 20 25 30 khz t 1 bridge mosfet switch on time t 1 selectable through spi. see figure 11. 375 1250 ns t 2 bridge mosfet switch on time t 2 selectable through spi. see figure 11. 1250 4750 ns t off bridge mosfet switch off time selectable through spi. see figure 11. 1250 4750 ns t switch_tol bridge mosfet switch on/off toler- ance ? 20 +20 % t open open circuit time out selectable through spi 0.32 163.84 ms topen_acc open circuit time out accuracy ? 20 +20 % t nocross non overlap time selectable through spi 0 1  s t nocross_acc non overlap accuracy ? 20 +20 %
amis ? 30421 http://onsemi.com 9 table 5. ac parameter the ac parameters are given for v bb and temperature in their operating ranges unless otherwise specified. symbol unit max typ min remark/test conditions parameter pin(s) digital inputs t nxt_hi nxt minimum, high pulse width see figure 6 625 ns t nxt_lo nxt minimum, low pulse width 625 ns t dir_set nxt set up time, following change of dir or 1  s t dir_hold nxt hold time, before change of dir or 1  s t slp_set set up time 300  s t slp_hold hold time 1  s t moten_set set up time 1  s t moten_ho ld hold time 1  s t msp update delay 1  s clear function t clr_set clr clear set up time see figure 7 40  s t clr clear duration time see figure 7 20 90  s digital outputs t h2l do, wdb, errb output fall ? time from v oh to v ol output type 2, capacitive load 400 pf and pull ? up resistor of 1.5 k  50 ns watchdog t wdpr prohibited watchdog acknowledge time 2.5 ms t wdto watchdog time out interval 32 512 ms t wdto_acc watchdog time out accuracy ? 20 +20 % t wdrd watchdog reset delay 500 ns serial peripheral interface (spi) t clk clk spi clock period see figure 8 1  s t clk_high spi clock high time 100 ns t clk_low spi clock low time 100 ns t di_set di spi data input set up time 50 ns t di_hold spi data input hold time 50 ns t cs_high csb spi chip select high time 2.5  s t cs_set spi chip select set up time 100 ns t cs_hold spi chip select hold time 100 ns speed and load angle output t sla_delay sla sla output update delay not ? transparent mode see figure 20 60  s t minsla minimum zero crossing time selectable through spi 40 360  s t minsla_acc minimum zero crossing accuracy ? 20 +20 % charge pump f cp cpn cpp charge pump frequency 160 200 250 khz t cpu motxx start ? up time of charge pump spec external components in table 4 250  s
amis ? 30421 http://onsemi.com 10 t t v ddh v dd t v bb v wdb t t por internal signal t wd timer internal signal ? ? ? ? ? figure 4. power ? on ? reset timing diagram t rf t por remarks : ? wdb ? pin pulled up to v dd ? t wdto = ? and are spi bits t pu t por t dspi t wdrd t wdpr or t wdto > t wdpr and t wdto figure 5. under ? and overvoltage t v bb v bboh v bbol v bbuh v bbul
amis ? 30421 http://onsemi.com 11 figure 6. digital input timing diagram dir or t nxt_hi t nxt_low t dir_set t moten_set t moten_hold t slp_set t slp_hold nxt ( = 1) nxt ( = 0) t msp t dir_hold remarks : ? , , , , and are spi bits ? timing for spi bits starts after cs is high ? t slp_set only relates to the digital inputs pins dir and nxt figure 7. clr ? pin timing diagram clr t clr_set t clr remarks : is any spi data figure 8. spi bus timing diagram clk di cs t clk t di_set t di_hold t cs_set t clk_high t clk_low t cs_hold t cs_high
amis ? 30421 http://onsemi.com 12 typical application schematic figure 9. typical application schematic amis ? 30421 t 1 t 2 t 3 t 4 r 1 t 5 t 6 t 7 t 8 r 2 m c 2 c 3 c 4 d 1 c 1 c 5 vdd v bat r 6 c 6 c 7 c 8 gnd gnd gnd amis ? 30421 vbb vcp cpp cpn 38 41 39 40 gxtr 7 gxtl 4 motxn 6 motxp 3 gxbl 2 gxbr 5 rsensxp 8 rsensxn 9 gytr 27 gytl 30 motyn 28 motyp 31 gybl 32 gybr 29 rsensyp 26 rsensyn 25 11 37 42 vdd 10 vregh 13 wd 17 nxt 23 dir 24 clr 16 sla 14 err 15 clk 18 cs 19 di 20 do 21 position feedback spi interface reset diagnostics motor positioner microcontroller table 6. external components list and description component function typ value tolerance unit c 1 v bb buffer capacitor (note 1) 100 20%  f c 2 charge ? pump pumping capacitor 220 20% nf c 3 charge ? pump buffer capacitor 220 20% nf c 4 v bb decoupling capacitor (note 2) 100 20% nf c 5 , c 8 v dd buffer capacitor 100 20 % nf c 6 low pass filter sla 1 20% nf c 7 vregh buffer capacitor 4.7 20% uf r 1 , r 2 sense resistors >25 1% m  r 6 low pass filter sla 5.6 1% k  d 1 optional reverse protection diode mbrd1045 t 1 t 8 h ? bridge n ? mosfet ntd4815n or ntd4813n or ntd40n03r or ntd5807n 10. esr < 1  . 11. esr < 50 m  .
amis ? 30421 http://onsemi.com 13 functional description h ? bridge pre ? drivers the h ? bridge pre ? drivers for external n ? type mosfets are controlled by means of current sources for slope regulation (figure 10). the current source value can be set through spi (see p35 and further). during the mosfet switch ? on and switch ? off phase this current source will be applied for a certain time (respectively t on and t off where t on is divided in t 1 and t 2 ). after this time (t on or t off ) the gate of the mosfet is pulled high or low by means of a switch (sw on or sw off ). the timings can also be set through spi (see p37 and further). to prevent short circuits, an additional time t nocross can be added between switching off one mosfet and switching on the other mosfet of a half h ? bridge (spi bits ). more information on the current sources and timings can be found in table 5. a detailed description of the spi settings for the h ? bridge pre ? drivers can be found at p31 and further. figure 11 gives a detailed view on the different stages during switching of the mosfet. i on i off sw on sw off amis ? 30421 external mosfet figure 10. pre ? driver topology v gate t 3 4 5 5 t on t off t 1 t 2 1 2 t nocross i on1 i on2 i off figure 11. detailed view on mosfet switching
amis ? 30421 http://onsemi.com 14 pwm current control a pwm comparator compares continuously the actual winding current (measured over the external sense resistor) with the requested current and feeds back the information to a digital regulation loop. this loop then generates a pwm signal, which turns on/off the current sources (i on , i off ) and switches (sw on , sw off ). the switching points of the pwm duty ? cycle are synchronized to the on ? chip pwm clock. the frequency of the pwm controller is fixed and will not vary with changes in the supply voltage. also variations in motor ? speed or load ? conditions of the motor have no ef fect. there are no external components required to adjust the pwm frequency. for emc reasons it?s possible to add jitter to the pwm by means of the bit. step translator and step mode the step translator provides the control of the motor by means of the stepmode spi bits , the enable spi bit , the direction spi bit and input pins dir and nxt. it is translating consecutive steps in corresponding currents in both motor coils for a given step mode. one out of 8 possible stepping modes can be selected through spi bits . after power ? up or clear (clr ? pin) the coil current translator is set to position 0. for all stepping modes except full step this means that the coil current is maximum in the y ? coil and zero in the x ? coil (see table 7). if nxt pulses are applied when the dir ? pin is pulled low, spi bit is zero and spi bit is one, the coil current translator will step through table 7 from top till bottom. if dir ? pin is pulled high or spi bit is set to ?1?, the coil current translator will step in opposite direction through the table. figures 12 up to 15 gives another view on the different stepping modes. the y ? coil current is plotted on the y ? axes, the x ? coil current on the x ? axes. notice that all stepping modes from t able 7 can be plotted on a circle with the exception of half step uncompensated and full step. these are plotted on a square. i y i x start = 0 step 1 step2 step 3 step 4 step5 step 6 step 7 dir ? pin = low figure 12. circular representation half ? step compensated dir ? pin = high i y i x start = 0 step 2 step 4 step 6 step 8 step 1 step 3 step5 step7 figure 13. circular representation 1/4 microstepping step 14 step12 step 10 step 15 step13 step 11 step 9 dir ? pin = low dir ? pin = high i y i x start= 0 step 1 step2 step 3 step4 step5 step 6 step7 dir ? pin = low figure 14. square representation half ? step uncompensated dir ? pin = high i y i x start= 0 step 1 step2 step3 dir ? pin = low dir ? pin = high figure 15. square representation full ? step remark: ? positive coil current flows from motxp to motxn and motyp to motyn. ? in above figures spi bit is set to ?0?. when set to ?1?, rotation will be reversed.
amis ? 30421 http://onsemi.com 15 table 7. circular translator table stepmode ( ) % of imax 000 001 010 011 100 101 110 111 coil x coil y 1/64 1/32 1/16 1/8 1/4 1/2 comp 1/2 uncomp full 0 0 0 0 0 0 0 ? 0 100 1 ? ? ? ? ? ? ? 3 100 2 1 ? ? ? ? ? ? 5 100 3 ? ? ? ? ? ? ? 8 100 4 2 1 ? ? ? ? ? 10 100 5 ? ? ? ? ? ? ? 13 100 6 3 ? ? ? ? ? ? 14 100 7 ? ? ? ? ? ? ? 17 98 8 4 2 1 ? ? ? ? 19 98 9 ? ? ? ? ? ? ? 22 98 10 5 ? ? ? ? ? ? 25 97 11 ? ? ? ? ? ? ? 27 97 12 6 3 ? ? ? ? ? 30 97 13 ? ? ? ? ? ? ? 32 95 14 7 ? ? ? ? ? ? 35 95 15 ? ? ? ? ? ? ? 37 94 16 8 4 2 1 ? ? ? 38 94 17 ? ? ? ? ? ? ? 41 92 18 9 ? ? ? ? ? ? 43 90 19 ? ? ? ? ? ? ? 46 90 20 10 5 ? ? ? ? ? 48 89 21 ? ? ? ? ? ? ? 51 87 22 11 ? ? ? ? ? ? 52 87 23 ? ? ? ? ? ? ? 54 86 24 12 6 3 ? ? ? ? 56 84 25 ? ? ? ? ? ? ? 59 83 26 13 ? ? ? ? ? ? 60 81 27 ? ? ? ? ? ? ? 62 79 28 14 7 ? ? ? ? ? 63 78 29 ? ? ? ? ? ? ? 67 76 30 15 ? ? ? ? ? ? 68 75 31 ? ? ? ? ? ? ? 70 73 32 16 8 4 2 1 1 1 71 / 100 71 / 100 33 ? ? ? ? ? ? ? 73 70 34 17 ? ? ? ? ? ? 75 68 35 ? ? ? ? ? ? ? 76 67 36 18 9 ? ? ? ? ? 78 63 37 ? ? ? ? ? ? ? 79 62 38 19 ? ? ? ? ? ? 81 60 39 ? ? ? ? ? ? ? 83 59 40 20 10 5 ? ? ? ? 84 56 41 ? ? ? ? ? ? ? 86 54 42 21 ? ? ? ? ? ? 87 52 43 ? ? ? ? ? ? ? 87 51 44 22 11 ? ? ? ? ? 89 48 45 ? ? ? ? ? ? ? 90 46 46 23 ? ? ? ? ? ? 90 43 47 ? ? ? ? ? ? ? 92 41 48 24 12 6 3 ? ? ? 94 38 49 ? ? ? ? ? ? ? 94 37 50 25 ? ? ? ? ? ? 95 35 51 ? ? ? ? ? ? ? 95 32 52 26 13 ? ? ? ? ? 97 30 53 ? ? ? ? ? ? ? 97 27 54 27 ? ? ? ? ? ? 97 25 55 ? ? ? ? ? ? ? 98 22 56 28 14 7 ? ? ? ? 98 19 57 ? ? ? ? ? ? ? 98 17 58 29 ? ? ? ? ? ? 100 14 59 ? ? ? ? ? ? ? 100 13 60 30 15 ? ? ? ? ? 100 10 61 ? ? ? ? ? ? ? 100 8 62 31 ? ? ? ? ? ? 100 5 63 ? ? ? ? ? ? ? 100 3
amis ? 30421 http://onsemi.com 16 table 7. circular translator table stepmode ( ) % of imax 000 coil y coil x 111 110 101 100 011 010 001 1/64 coil y coil x full 1/2 uncomp 1/2 comp 1/4 1/8 1/16 1/32 64 32 16 8 4 2 2 ? 100 0 65 ? ? ? ? ? ? ? 100 ? 3 66 33 ? ? ? ? ? ? 100 ? 5 67 ? ? ? ? ? ? ? 100 ? 8 68 34 17 ? ? ? ? ? 100 ? 10 69 ? ? ? ? ? ? ? 100 ? 13 70 35 ? ? ? ? ? ? 100 ? 14 71 ? ? ? ? ? ? ? 98 ? 17 72 36 18 9 ? ? ? ? 98 ? 19 73 ? ? ? ? ? ? ? 98 ? 22 74 37 ? ? ? ? ? ? 97 ? 25 75 ? ? ? ? ? ? ? 97 ? 27 76 38 19 ? ? ? ? ? 97 ? 30 77 ? ? ? ? ? ? ? 95 ? 32 78 39 ? ? ? ? ? ? 95 ? 35 79 ? ? ? ? ? ? ? 94 ? 37 80 40 20 10 5 ? ? ? 94 ? 38 81 ? ? ? ? ? ? ? 92 ? 41 82 41 ? ? ? ? ? ? 90 ? 43 83 ? ? ? ? ? ? ? 90 ? 46 84 42 21 ? ? ? ? ? 89 ? 48 85 ? ? ? ? ? ? ? 87 ? 51 86 43 ? ? ? ? ? ? 87 ? 52 87 ? ? ? ? ? ? ? 86 ? 54 88 44 22 11 ? ? ? ? 84 ? 56 89 ? ? ? ? ? ? ? 83 ? 59 90 45 ? ? ? ? ? ? 81 ? 60 91 ? ? ? ? ? ? ? 79 ? 62 92 46 23 ? ? ? ? ? 78 ? 63 93 ? ? ? ? ? ? ? 76 ? 67 94 47 ? ? ? ? ? ? 75 ? 68 95 ? ? ? ? ? ? ? 73 ? 70 96 48 24 12 6 3 3 2 71 / 100 ? 71 / ? 100 97 ? ? ? ? ? ? ? 70 ? 73 98 49 ? ? ? ? ? ? 68 ? 75 99 ? ? ? ? ? ? ? 67 ? 76 100 50 25 ? ? ? ? ? 63 ? 78 101 ? ? ? ? ? ? ? 62 ? 79 102 51 ? ? ? ? ? ? 60 ? 81 103 ? ? ? ? ? ? ? 59 ? 83 104 52 26 13 ? ? ? ? 56 ? 84 105 ? ? ? ? ? ? ? 54 ? 86 106 53 ? ? ? ? ? ? 52 ? 87 107 ? ? ? ? ? ? ? 51 ? 87 108 54 27 ? ? ? ? ? 48 ? 89 109 ? ? ? ? ? ? ? 46 ? 90 110 55 ? ? ? ? ? ? 43 ? 90 111 ? ? ? ? ? ? ? 41 ? 92 112 56 28 14 7 ? ? ? 38 ? 94 113 ? ? ? ? ? ? ? 37 ? 94 114 57 ? ? ? ? ? ? 35 ? 95 115 ? ? ? ? ? ? ? 32 ? 95 116 58 29 ? ? ? ? ? 30 ? 97 117 ? ? ? ? ? ? ? 27 ? 97 118 59 ? ? ? ? ? ? 25 ? 97 119 ? ? ? ? ? ? ? 22 ? 98 120 60 30 15 ? ? ? ? 19 ? 98 121 ? ? ? ? ? ? ? 17 ? 98 122 61 ? ? ? ? ? ? 14 ? 100 123 ? ? ? ? ? ? ? 13 ? 100 124 62 31 ? ? ? ? ? 10 ? 100 125 ? ? ? ? ? ? ? 8 ? 100 126 63 ? ? ? ? ? ? 5 ? 100 127 ? ? ? ? ? ? ? 3 ? 100
amis ? 30421 http://onsemi.com 17 table 7. circular translator table stepmode ( ) % of imax 000 coil y coil x 111 110 101 100 011 010 001 1/64 coil y coil x full 1/2 uncomp 1/2 comp 1/4 1/8 1/16 1/32 128 64 32 16 8 4 4 ? 0 ? 100 129 ? ? ? ? ? ? ? ? 3 ? 100 130 65 ? ? ? ? ? ? ? 5 ? 100 131 ? ? ? ? ? ? ? ? 8 ? 100 132 66 33 ? ? ? ? ? ? 10 ? 100 133 ? ? ? ? ? ? ? ? 13 ? 100 134 67 ? ? ? ? ? ? ? 14 ? 100 135 ? ? ? ? ? ? ? ? 17 ? 98 136 68 34 17 ? ? ? ? ? 19 ? 98 137 ? ? ? ? ? ? ? ? 22 ? 98 138 69 ? ? ? ? ? ? ? 25 ? 97 139 ? ? ? ? ? ? ? ? 27 ? 97 140 70 35 ? ? ? ? ? ? 30 ? 97 141 ? ? ? ? ? ? ? ? 32 ? 95 142 71 ? ? ? ? ? ? ? 35 ? 95 143 ? ? ? ? ? ? ? ? 37 ? 94 144 72 36 18 9 ? ? ? ? 38 ? 94 145 ? ? ? ? ? ? ? ? 41 ? 92 146 73 ? ? ? ? ? ? ? 43 ? 90 147 ? ? ? ? ? ? ? ? 46 ? 90 148 74 37 ? ? ? ? ? ? 48 ? 89 149 ? ? ? ? ? ? ? ? 51 ? 87 150 75 ? ? ? ? ? ? ? 52 ? 87 151 ? ? ? ? ? ? ? ? 54 ? 86 152 76 38 19 ? ? ? ? ? 56 ? 84 153 ? ? ? ? ? ? ? ? 59 ? 83 154 77 ? ? ? ? ? ? ? 60 ? 81 155 ? ? ? ? ? ? ? ? 62 ? 79 156 78 39 ? ? ? ? ? ? 63 ? 78 157 ? ? ? ? ? ? ? ? 67 ? 76 158 79 ? ? ? ? ? ? ? 68 ? 75 159 ? ? ? ? ? ? ? ? 70 ? 73 160 80 40 20 10 5 5 3 ? 71 / ? 100 ? 71 / ? 100 161 ? ? ? ? ? ? ? ? 73 ? 70 162 81 ? ? ? ? ? ? ? 75 ? 68 163 ? ? ? ? ? ? ? ? 76 ? 67 164 82 41 ? ? ? ? ? ? 78 ? 63 165 ? ? ? ? ? ? ? ? 79 ? 62 166 83 ? ? ? ? ? ? ? 81 ? 60 167 ? ? ? ? ? ? ? ? 83 ? 59 168 84 42 21 ? ? ? ? ? 84 ? 56 169 ? ? ? ? ? ? ? ? 86 ? 54 170 85 ? ? ? ? ? ? ? 87 ? 52 171 ? ? ? ? ? ? ? ? 87 ? 51 172 86 43 ? ? ? ? ? ? 89 ? 48 173 ? ? ? ? ? ? ? ? 90 ? 46 174 87 ? ? ? ? ? ? ? 90 ? 43 175 ? ? ? ? ? ? ? ? 92 ? 41 176 88 44 22 11 ? ? ? ? 94 ? 38 177 ? ? ? ? ? ? ? ? 94 ? 37 178 89 ? ? ? ? ? ? ? 95 ? 35 179 ? ? ? ? ? ? ? ? 95 ? 32 180 90 45 ? ? ? ? ? ? 97 ? 30 181 ? ? ? ? ? ? ? ? 97 ? 27 182 91 ? ? ? ? ? ? ? 97 ? 25 183 ? ? ? ? ? ? ? ? 98 ? 22 184 92 46 23 ? ? ? ? ? 98 ? 19 185 ? ? ? ? ? ? ? ? 98 ? 17 186 93 ? ? ? ? ? ? ? 100 ? 14 187 ? ? ? ? ? ? ? ? 100 ? 13 188 94 47 ? ? ? ? ? ? 100 ? 10 189 ? ? ? ? ? ? ? ? 100 ? 8 190 95 ? ? ? ? ? ? ? 100 ? 5 191 ? ? ? ? ? ? ? ? 100 ? 3
amis ? 30421 http://onsemi.com 18 table 7. circular translator table stepmode ( ) % of imax 000 coil y coil x 111 110 101 100 011 010 001 1/64 coil y coil x full 1/2 uncomp 1/2 comp 1/4 1/8 1/16 1/32 192 96 48 24 12 6 6 ? ? 100 0 193 ? ? ? ? ? ? ? ? 100 3 194 97 ? ? ? ? ? ? ? 100 5 195 ? ? ? ? ? ? ? ? 100 8 196 98 49 ? ? ? ? ? ? 100 10 197 ? ? ? ? ? ? ? ? 100 13 198 99 ? ? ? ? ? ? ? 100 14 199 ? ? ? ? ? ? ? ? 98 17 200 100 50 25 ? ? ? ? ? 98 19 201 ? ? ? ? ? ? ? ? 98 22 202 101 ? ? ? ? ? ? ? 97 25 203 ? ? ? ? ? ? ? ? 97 27 204 102 51 ? ? ? ? ? ? 97 30 205 ? ? ? ? ? ? ? ? 95 32 206 103 ? ? ? ? ? ? ? 95 35 207 ? ? ? ? ? ? ? ? 94 37 208 104 52 26 13 ? ? ? ? 94 38 209 ? ? ? ? ? ? ? ? 92 41 210 105 ? ? ? ? ? ? ? 90 43 211 ? ? ? ? ? ? ? ? 90 46 212 106 53 ? ? ? ? ? ? 89 48 213 ? ? ? ? ? ? ? ? 87 51 214 107 ? ? ? ? ? ? ? 87 52 215 ? ? ? ? ? ? ? ? 86 54 216 108 54 27 ? ? ? ? ? 84 56 217 ? ? ? ? ? ? ? ? 83 59 218 109 ? ? ? ? ? ? ? 81 60 219 ? ? ? ? ? ? ? ? 79 62 220 110 55 ? ? ? ? ? ? 78 63 221 ? ? ? ? ? ? ? ? 76 67 222 111 ? ? ? ? ? ? ? 75 68 223 ? ? ? ? ? ? ? ? 73 70 224 112 56 28 14 7 7 0 ? 71 / ? 100 71 / 100 225 ? ? ? ? ? ? ? ? 70 73 226 113 ? ? ? ? ? ? ? 68 75 227 ? ? ? ? ? ? ? ? 67 76 228 114 57 ? ? ? ? ? ? 63 78 229 ? ? ? ? ? ? ? ? 62 79 230 115 ? ? ? ? ? ? ? 60 81 231 ? ? ? ? ? ? ? ? 59 83 232 116 58 29 ? ? ? ? ? 56 84 233 ? ? ? ? ? ? ? ? 54 86 234 117 ? ? ? ? ? ? ? 52 87 235 ? ? ? ? ? ? ? ? 51 87 236 118 59 ? ? ? ? ? ? 48 89 237 ? ? ? ? ? ? ? ? 46 90 238 119 ? ? ? ? ? ? ? 43 90 239 ? ? ? ? ? ? ? ? 41 92 240 120 60 30 15 ? ? ? ? 38 94 241 ? ? ? ? ? ? ? ? 37 94 242 121 ? ? ? ? ? ? ? 35 95 243 ? ? ? ? ? ? ? ? 32 95 244 122 61 ? ? ? ? ? ? 30 97 245 ? ? ? ? ? ? ? ? 27 97 246 123 ? ? ? ? ? ? ? 25 97 247 ? ? ? ? ? ? ? ? 22 98 248 124 62 31 ? ? ? ? ? 19 98 249 ? ? ? ? ? ? ? ? 17 98 250 125 ? ? ? ? ? ? ? 14 100 251 ? ? ? ? ? ? ? ? 13 100 252 126 63 ? ? ? ? ? ? 10 100 253 ? ? ? ? ? ? ? ? 8 100 254 127 ? ? ? ? ? ? ? 5 100 255 ? ? ? ? ? ? ? ? 3 100 remarks : ? positive coil current conducts from motxp to motxn or motyp to motyn. ? for some microstep positions 2 values are given for coil x and coil y. the second value is only valid for = ?11x?
amis ? 30421 http://onsemi.com 19 direction the direction of rotation can be changed by means of the dir ? pin and the spi bit . see also figure 12 up to figure 15. setup and hold times need to be respected when changing direction (see figure 6). nxt input every rising or falling edge on the nxt ? pin (selectable through spi bit ) will move the coil current one step up or down (dependant on the dir ? pin and bit) in the translator table (see table 7). the motor current will be updated at the next pwm cycle. enable the enable spi bit is used to enable the pwm regulator and drive coil current through the stepper motor coils. when ?1? the motor driver is enabled and coil current will be conducted. if ?0? (zero), the h ? bridge drivers are disabled. when the motor driver is enabled, the nxt ? and dir ? pin as also the spi bit can be used to control the movement of the stepper motor. it?s not allowed to apply pulses on the nxt ? pin when the motor driver is disabled. certain errors (see error output p24) will automatically disable the motor driver ( = 0). the errors first need to be cleared before one is able to enable the motor driver again. setup and hold times need to be respected (see figure 6). microstep position to be able to track the position in the current translator table (table 7), the microstep position spi byte can be used (). this byte gives the position within the current translator table in units of 1/64 microsteps. this means that when working in 1/4 th microstepping the read out microstep positions will be 0, 16, 32, ... the microstep position can be used to track/verify the real position of the stepper motor and as a reference point for changing the stepping mode (to avoid phase shift (see further)). see also application note and8399 for more information on this (this application note is based on amis ? 305xx but is similar for amis ? 30421). keep in mind that will only be update 1  s after the nxt pulse was applied. v dir t v nxt t step up in translator table step up in translator table step down in translator table step down in translator table figure 16. translator table update microstep is used to set the microstep stepping mode. changing to another microstep stepping mode can be done but the setup and hold timings need to be respected (see figure 6). additionally, one needs to be careful to not introduce an offset (or phase shift) in the translator table. increasing to a higher stepping mode (e.g. from 1/2 to 1/4) can be done at any moment without introducing an offset or phase shift. decreasing to a lower stepping mode (e.g. from 1/4 to 1/2) can introduce an of fset or phase shift if the change to the lower stepping mode is not done at the right moment. one needs to make sure that the translator table position is shared both by the old and new stepping mode setting. figure 17 gives a good and bad example of reducing the stepping mode. to avoid the creation of an offset it?s advised to only change the stepping mode at a full ? step position ( equal to 0, 64, 128 or 192). changing the stepping mode to (or from) full step stepping mode also needs to be done with care. changing to full step mode at the moment the coil current is 100% in one of the coils will result in a movement of the rotor. reversed, changing from full step to any other stepping mode will also result in a movement of the rotor (see figure 18, top left). if the stepping mode is changed to full step when the coil current in both coils is 71%, the coil current in both coils will only be 71% in full step stepping mode instead of 100% (see figure 18, top right). changing to full step stepping mode when the coil current in one of the coils is not 100% nor 71% will result in an offset (see figure 18, bottom). notice that stepping is now done on a rectangle instead of a square. there will always be coil current present in both coils when working in full step stepping mode (see table 7). when zero current is requested in one of the coils, half step stepping mode can be used to mimic full step (see section full step stepping mode in application note and8399/d for more info).
amis ? 30421 http://onsemi.com 20 i y i x step 1 step 2 step 3 dir ? pin = low i y i x step 2 1/4 th stepping mode half step correct change to a lower stepping mode. step 2 of 1/4 th stepping mode is equal to step 1 of half step stepping mode (see table 7). no offset or phase shift is created. i y i x dir pin = low i y i x step 1 1/4 th stepping mode half step incorrect change to a lower stepping mode. step 1 of 1/4 th stepping mode is not shared with a step in half step stepping mode (see table 7). an offset or phase shift will be created! figure 17. nxt ? step mode synchronization i y i x step i y i x step half step full step i y i x step i y i x step half step full step i y i x step i y i x step half step full step figure 18. changing to/from full step stepping mode programmable peak ? current the amplitude of the current waveform in the motor coils (i max ) can be programmed through spi bits . the coil current can be calculated as next: i max   r sense r sense is resistor r 1 and r 2 as given in figure 9. a change in the coil current () will be updated at the next pwm cycle. clear logic 0 on the clr ? pin allows normal operation of the chip. to clear the complete digital inside amis ? 30421, the clr ? pin needs to be pulled to logic 1 for a minimum time of t clr (table 5). clearing the motor driver can not be done during sleep mode. during a clear the charge pump remains active. the voltage regulator remains functional during and after the clear action and the wdb ? pin is not activated. after a clear, nxt pulses can be applied after t clr_set (see figure 7). speed and load angle output the sla ? pin provides an output voltage that indicates the level of the bemf (back electro magnetic force) voltage of the motor. this bemf voltage is sampled during every so ? called ?coil current zero crossing?. per coil, two zero ? current positions exist per electrical period, yielding in a total of four zero ? current observation points per electrical period. because of the relatively high recirculation currents in the coil during current decay, the coil voltage v coil shows a
amis ? 30421 http://onsemi.com 21 transient behavior. this transient behavior (which is not the bemf) can be made visible or invisible on the sla ? pin by means of spi bit . when set to transparent ( = ?1?), the coil voltage is sampled every pwm cycle and updated on the sla ? pin (see figure 19). when set to not ? transparent ( = ?0?), only the last sample (taken right before leaving the ?coil current zero crossing?) will be copied to the sla ? pin (see figure 20). when working in not ? transparent mode ( = ?0?) keep in mind that there is a delay between applying the nxt pulse (to leave the ?coil current zero crossing?) and the updated voltage on the sla ? pin (see t sla_delay in figure 20 and table 5). v sla t bemf of previous zero crossing transparent t i coil i coil t coil current zero crossing previous microstep next microstep v coil t v bb +0.6v v bemf current decay ne xt step ne xt step v nxt t remark: v coil is only drawn during the coil current zero crossing figure 19. principle of bemf measurement in transparent mode v sla t last sample before leaving zero crossing is retained. bemf of previous zero crossing t sla _delay not ? transparent t i coil i coil t coil current zero crossing previous microstep next microstep v coil t v bb +0.6v v bemf current decay ne xt step ne xt step v nxt t remark: v coil is only drawn during the coil current zero crossing figure 20. principle of bemf measurement in not ? transparent mode the relationship between the voltage measured on the sla ? pin and the coil voltage is: v sla = 0.6 + (0.6 x ) + (v coil x ) spi bit can be used to add an additional offset of 0.6 v. five different sla gain values can be set by means of spi bits . amis ? 30421 has the ability to stretch the ?coil current zero crossing?. if nxt pulses are applied too fast it?s possible that the ?coil current zero crossing? is too short making it impossible to measure the real bemf (see figure 21). by using spi bits one can stretch the ?coil current zero crossing? without changing the speed of the motor (see figure 21). amis ? 30421 will ignore but keep track of the nxt pulses applied during the ?stretched coil current zero crossing? and compensate the ignored pulses when leaving the ?coil current zero crossing?. more information on using the sla ? pin can be found in application note and8399. although this application note refers to amis ? 305xx, it is also valid for amis ? 30421.
amis ? 30421 http://onsemi.com 22 figure 21. bemf sampling without (left) and with (right) zero crossing stretching sleep mode amis ? 30421 can be placed in sleep mode by means of spi bit . this mode allows reduction of current ? consumption when the motor is not in operation. the effect of sleep mode is as follows: ? the drivers are put in hiz ? all analog circuits are disabled and in low ? power mode ? all spi registers maintain their logic content ? spi communication is still possible (slightly current increase during spi communication). ? status registers can not be cleared by reading out ? nxt and dir inputs are forbidden ? oscillator and digital clocks are silent ? motor driver can not be cleared by means of the clr ? pin the voltage regulator remains active but with reduced current ? output capability (i load_pd ). when sleep mode is left a start ? up time is needed for the charge pump to stabilize. after this time (t slp_set ) nxt commands can be issued (see also figure 6). enabling the motor when the charge pump is not stable can result in overcurrent errors (see section over ? current detection ). because of this it?s advised to keep the motor disabled during the stabilization time (t slp_set ). the io ? pins of amis ? 30421 have internal pull ? down or pull ? up resistors (see figure 3). keep this in mind when entering sleep mode. in sleep mode v dd can drop to 2.1 v minimum (see v dd_sleep in table 4). keep in mind that in this case it?s not allowed to pull the input pins above 2.1 v!
amis ? 30421 http://onsemi.com 23 warning, error detection and diagnostics feedback thermal warning and shutdown amis ? 30421 has 4 thermal ranges which can be read out through spi bits and . thermal range 1 goes from ? 40 c up to t 1 . thermal range 2 goes from t 1 to t 2 and thermal range 3 goes from t 2 up to t 3 (t 1 , t 2 and t 3 can be found in table 4). once above t 3 the 4 th thermal level is reached which is the thermal warning range. when junction temperature rises above t tw (= t 3 ), the errb ? pin will be activated. if junction temperature increases above thermal shutdown level (t tsd ), then the circuit goes in thermal shutdown mode and all driver transistors are disabled (high impedance). the condition to get out of the thermal shutdown mode is to be at a temperature lower than t tw and by clearing the spi bit. ? 40 c t 1 ?? ?? ?? ?? ?? aa aa ? pin active) thermal range 3 thermal range 2 thermal range 1 figure 22. thermal ranges over ? current detection the over ? current detection circuit monitors the load current in each activated output stage. if the load current exceeds the over ? current detection threshold, the errb ? pin will be activated and the drivers are switched off (motor driver disabled) to reduce the power dissipation and to protect the h ? bridge. each driver has an individual detection bit (see status register 1 and 2). the error condition is latched and the microcontroller needs to read out the error to reset the error and to be able to re ? enable the motor driver again. note: successive resetting the motor driver in case of a short circuit condition may damage the drivers. open coil/current not reached detection open coil detection is based on the observation of 100% duty cycle of the pwm regulator. if in a coil 100% duty cycle is detected for a certain time, an open coil will be latched (see status reg ister 1 and 2) and the errb ? pin will be activated (drivers are disabled). the time this 100% duty cycle needs to be present is adjustable with spi bits . a short time will result in fast detection of an open ? coil but could also trigger unwanted open ? coil errors. increase the timing if this is the case. when the resistance of a motor coil is very large and the supply voltage is low , it can happen that the motor driver is not able to deliver the requested current to the motor. under these conditions the pwm controller duty cycle will be 100% and the errb ? pin will flag this situation. this feature can be used to test if the operating conditions (supply voltage, motor coil resistance) still allow reaching the requested coil ? current or else the coil current should be reduced. note: a short circuit could trigger an open coil. charge pump failure the charge pump is an important circuit that guarantees low r ds(on) for all external mosfet?s, especially for low supply voltages. if supply voltage is too low or external components are not properly connected to guarantee a low r ds(on) of the drivers, a charge pump failure is latched (), the errb ? pin is activated and the driver is disabled ( = ?0?). one needs to read status register 1 to clear the charge pump failure. after power on reset (por) the charge pump voltage will need some time to exceed the required threshold. during that time the errb ? pin will be active but not latched for 250us. if the slope of the power supply v bb is slow during power up (charge pump not started after 250  s), a charge pump failure will be latched and the errb ? pin is activated (see also figure 23).
amis ? 30421 http://onsemi.com 24 v bb t v errb t charge pump failure during start up charge pump failure longer than 250 us due to slow voltage slope error is latched. figure 23. charge pump failure watchdog when v bb is applied, the wdb ? pin is kept low for t por (table 5). this can for instance be used to reset an external microcontroller at power up. the wdb ? pin also has a second function, a watchdog function. when the watchdog is enabled ( = ?1?), a timer will start counting up. when the counter reaches a certain value (), the spi bit will be set and the wdb ? pin will be pulled low for a time equal to t por to reset the external microcontroller. to avoid that the microcontroller gets reset, the microcontroller needs to re ? enable the watchdog before the count value is reached (= write ?1? to before is reached). this functionality can be used to reset a ?stuck? microcontroller. the spi bit can be used to detect a cold or warm boot. when powering the application (cold boot), will be zero. if the microcontroller has been reset by the wdb ? pin (warm boot), bit will be ?1?. the microcontroller can use this information to detect a cold or warm boot. it?s forbidden to re ? enable the watchdog too fast (minimum time between re ? enabling must be above t wdpr (see figure 4)). one may also not enable the watchdog too fast after power up (see t dspi , figure 4). a small analogue filter avoids resetting due to spikes or noise on the vdd supply (t rf ). during and after power up the wdb ? pin is an open drain output. one can change this to a push ? pull output by using spi bit . error output the error output (errb ? pin) will be activated if an error is reported. next errors will be reported: ? thermal warning ? thermal shutdown ? overcurrent ? open coil ? charge pump failure ? all errors except a thermal warning will disable the h ? bridge drivers to protect the motor driver ( = ?0?). to reset the error one needs to read out the error. only when all errors are reset it will be possible to re ? enable the motor driver ( = ?1?). keep in mind that during power up a charge pump failure will be reported during the first 250us but will not be latched (see also charge pump failure ). during and after power up the errb ? pin is an open drain output. one can change this to a push ? pull output with spi bit .
amis ? 30421 http://onsemi.com 25 power supply and thermal calculation logic supply regulator amis ? 30421 has an on ? chip 3.3v low ? drop regulator to supply the digital part of the chip itself, some low ? voltage analog blocks and external circuitry. see table 4 for the limitations. over ? and undervoltage amis ? 30421 has undervoltage detection. if v bb drops below v bbul , the drivers are disabled. to be able to enable the drivers again the v bb voltage needs to rise above v bbuh . overvoltage detection is also present. if the voltage rises above v bboh the drivers are disabled. the voltage needs to drop below v bbol to be able to enable the driver again. see also figure 5. start ? up behavior figure 4 gives the start ? up of amis ? 30421. after v bb is applied and after a certain power up time (t pu ), the internal voltage regulator v dd will start ? up. when v dd gets above v ddh , the internal por will be released and the digital will start ? up. the wdb ? pin will be kept low for an additional 100ms (t por ). after the wdb ? pin is deactivated and after a time t dspi , spi communication can be initiated. junction temperature calculation to calculate the junction temperature of amis ? 30421 the thermal resistance junction ? to ? ambient must be known. when only a pcb heat sink is used, a typical value is 30 c/w (see table 4). there are three modes the junction temperature can be calculated for. ? in sleep mode ( = ?1?) the v bat consumption is maximum 150  a making t j = t amb . ? in normal mode when the driver is disabled ( = ?0?), the v bat consumption is maximum 20 ma (no external load on vdd ? pin). the junction temperature can be calculated as next: t j  t a   v bat  i bat  rth ja  for an 18 v application operating at an ambient temperature of 125 c this would give: t j  125 c   18 v  20 ma  30 c  w  t j  135.8 c ? in normal mode with the driver enabled ( = ?1?) the gate charge current needs to be included in the calculations. i bat  20 ma   6  v regh  c iss  f pwm  for an 18 v application driving external mosfet?s with an input capacitance of 1 nf this would result in: i bat  20 ma   6  12.8 v  1nf  30 khz  i bat  22.3 ma operating at 125 c ambient temperature this result in a junction temperature of: t j  125 c   18 v  22.3 ma  30 c  w  t j  137 c
amis ? 30421 http://onsemi.com 26 spi interface the serial peripheral interface (spi) allows an external microcontroller (master) to communicate with amis ? 30421. the implemented spi block is designed to interface directly with numerous microcontrollers from several manufacturers. amis ? 30421 acts always as a slave and can?t initiate any transmission. the operation of the device is configured and controlled by means of spi registers which are observable for read and/or write from the master. spi transfer format and pin signals during a spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (clk) synchronizes shifting and sampling of the information on the two serial data lines (do and di). do signal is the output from the slave (amis ? 30421), and di signal is the output from the master. a chip select line (csb) allows individual selection of a slave spi device in a multiple ? slave system. the csb line is active low. if amis ? 30421 is not selected, do is in hiz and does not interfere with spi bus activity. the ou tput type of do can be set in spi (). since amis ? 30421 operates as a slave in mode 0 (cpol = 0; cpha = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. the master spi port must be configured in mode 0 too, to match this operation. the diagram below is both a master and a slave timing diagram since clk, do and di pins are directly connected between the master and the slave. ?? ?? ??? ??? ???? ???? clk di cs msb 6 5 4 3 2 1 lsb msb 6 5 4 3 2 1 lsb do 7 8 5 6 3 4 1 2 figure 24. timing diagram of a spi transfer transfer packet serial data transfer is assumed to follow msb first rule. the transfer packet contains one or more bytes. byte 1 contains the command and the spi register address and indicates to amis ? 30421 the chosen type of operation and addressed register. byte 2 contains data, or sent from the master in a write operation, or received from amis ? 30421 in a read operation. two command types can be distinguished in the communication between master and amis ? 30421: ? cmd2 = ?0?: read from spi register with address addr[4:0] ? cmd2 = ?1?: write to spi register with address addr[4:0] command and spi register address cmd2 cmd1 cmd0 addr4 addr3 addr2 addr1 addr0 msb lsb command spi register address byte1 data d7 d6 d5 d4 d3 d2 d1 d0 msb lsb byte2 figure 25. spi transfer packet read operation if the master wants to read data from a status or control register, it initiates the communication by sending a read command. this read command contains the address of the spi register to be read out. at the falling edge of the eight clock pulse the data ? out shift register is updated with the content of the corresponding internal spi register . in the next 8 ? bit clock pulse train this data is shifted out via do pin. at the same time the data shifted in from di (master) should be interpreted as the following successive command or dummy data. status register 0, 1 and 2 (see spi registers) contain 7 data bits and a parity check bit. the most significant bit (d7) represents a parity of d[6:0]. if the number of logical ones in d[6:0] is odd, the parity bit d7 equals ?1?. if the number of logical ones in d[6:0] is even then the parity bit d7 equals
amis ? 30421 http://onsemi.com 27 ?0?. this simple mechanism protects against noise and increases the consistency of the transmitted data. if a parity check error occurs it is recommended to initiate an additional read command to obtain the status again. the csb ? pin is active low and may remain low between successive read commands as illustrated in figure 28. there is one exception. in case an error condition occurs the root cause of the problem can be determined by reading out the status registers. however, if the error occurs at the moment csb is low, one first needs to pull csb high to update the status registers properly. only then the status registers can be read out to determine the error. for this reason it is also recommended to keep csb high when the spi bus is idle. ?? ?? ?? ??? clk di cs 0 0 0 addr[4] addr[3] addr[2] addr[1] addr[0] old data or not valid do command or dummy old data or not valid old data or not valid old data or not valid old data or not valid old data or not valid old data or not valid old data or not valid command or dummy command or dummy command or dummy command or dummy command or dummy command or dummy command or dummy d[7] from addr d[6 ] from addr d[5] from addr d[4 ] from addr d[3] from addr d[2 ] from addr d[1] from addr d[0 ] from addr data from previous command or not valid after por . next command or dummy data figure 26. single read operation where data from spi register is read by the master write operation if the master wants to write data to a control register it initiates the communication by sending a write command. this contains the address of the spi register to write to. the command is followed with a data byte. this incoming data will be stored in the corresponding control register after csb goes from low to high. it is important that the writing action to the control register is exactly 16 bits long and that csb goes high after these 16 bits. if more or less bits are transmitted the complete transfer packet is ignored. a write command executed for a read ? only register (e.g. status registers) will not affect the addressed register and the device operation. amis ? 30421 responds on every incoming byte by shifting out via do the data stored in the last received address. because after a power ? on ? reset the initial address is unknown the data shifted out via do is not valid. ?? ?? ?? ?? ??? ??? figure 27. single write operation where data from the master is written in spi register examples of read and write operations in the following examples successive read and/or write operations are combined. in figure 28 the master first reads the status from register at addr1 and at addr2 followed by writing a control byte in control register at addr3. note that during the write command the old data of the pointed register is returned at the moment the new data is shifted in. di cs do read data from addr1 read data from addr2 write data to addr3 new data to addr 3 old data or not valid data from addr1 data from addr2 old data from addr3 data from previous command or not valid after por new data is written into register with addr3 at rising edge of csb figure 28. 2 successive read commands followed by a write command after a write operation the master could initiate a read command in order to verify the data correctly written as illustrated in figure 29. during reception of the read command the old data is returned for a second time. only after receiving the read command the new data is transmitted. this rule also applies when the master device
amis ? 30421 http://onsemi.com 28 wants to initiate an spi transfer to read the status registers. because the internal system clock updates the status registers only when csb line is high, the first read out byte might represent old status information (figure 30). di do cs write data to addr4 new data for addr4 read data from addr4 command or dummy old data or not valid old data from addr4 old data from addr4 new data from addr4 data from previous command or not valid after por new data is written into register with addr4 at rising edge of csb figure 29. write operation followed by a read operation to verify di cs do read from 0x04 read from 0x05 read from 0x06 command or dummy old data or not valid data from 0x04 data from 0x05 data from 0x06 data from previous command or not valid after por figure 30. 3 read operations in a row bad examples of read and write operations the following example demonstrates a bad write operation. after a write operation a read operation is done before csb is made high. the data will not be written in the register. figure 32 demonstrates how it should be done (see also figure 29). the second example (figure 33) demonstrates an incorrect way of reading errors. after a write operation the errb ? pin toggles indication an error . without toggling csb the 3 status registers are read out to determine the error. because csb was not high after the error was detected, the status registers will not be updated and the error can not be determined. a second problem with figure 33 is that the data written to addr9 will not be stored because csb was not toggled after the write operation. figure 34 gives the correct way of reading out errors. when the error is detected (toggling of errb ? pin), csb is made high to make sure the status registers are updated. then the status registers are read out. notice that errb toggles after status register 1 is read out (addr 0x05). this indicates that the error was an overcurrent in the x ? coil, a charge pump failure or an open x ? coil. also notice that because csb is made high after the write operation, the write operation will now be done correctly. di cs do write data to addr8 new data for addr8 read data from addr8 command or dummy old data or not valid old data from addr8 old data from addr8 old data from addr8 read data from addr8 command or dummy old data from addr8 old data from addr8 data from previous command or not valid after por new data is not written into register because write operation did not ended with csb going high ! data was not written in addr8 because write operation did not ended with csb going high ! figure 31. bad example of write operation
amis ? 30421 http://onsemi.com 29 di cs do write data to addr8 new data for addr8 old data or not valid old data from addr8 read data from addr8 command or dummy old data from addr8 new data from addr8 data from previous command or not valid after por figure 32. good write operation di cs do write data to addr9 new data for addr9 read data from 0x04 old data or not valid old data from addr9 old data from addr9 old data from 0x04 read data from 0x05 old data from 0x05 read data from 0x06 old data from 0x06 new command or dummy err data from previous command or not valid after por figure 33. bad example of error read out di cs do write data to addr9 new data for addr9 read data from 0x04 old data or not valid old data from addr9 old data from addr9 new data from 0x04 read data from 0x05 new data from 0x05 read data from 0x06 new data from 0x06 new command or dummy err data from previous command or not valid after por making csb high will update the status registers figure 34. correct read out of error spi register description below table gives an overview of all spi registers that can be used. table 8. spi register overview spi register address access abbreviation watchdog register 0x00 r/w wr control register 0 0x01 r/w cr0 control register 1 0x02 r/w cr1 control register 2 0x03 r/w cr2 status register 0 0x04 r sr0 status register 1 0x05 r sr1 status register 2 0x06 r sr2 status register 3 0x07 r sr3 predriver register 0 0x09 r/w pdrv0
amis ? 30421 http://onsemi.com 30 table 8. spi register overview spi register abbreviation access address predriver register 1 0x0a r/w pdrv1 predriver register 2 0x0b r/w pdrv2 predriver register 3 0x0c r/w pdrv3 predriver register 4 0x0d r/w pdrv4 predriver register 5 0x0e r/w pdrv5 predriver register 6 0x0f r/w pdrv6 predriver register 7 0x10 r/w pdrv7 where: r/w = read and write access, r = read access only watchdog register (wr) the watchdog register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time ? out. it can also be used to set the short circuit and open coil detection time ? out. table 9. watchdog register watchdog register (wr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 1 0 0 data wden wdt[3:0] open_coil[1:0] ? table 10. watchdog register parameters parameter value value description info wden 0 disable enables the watchdog p24 1 enable wdt[3:0] 0000 32 ms defines the watchdog time ? out period. the watchdog needs to be re ? enabled (wden) within this time or wdb ? pin is ac- tivated for t por . p24 0001 64 ms 0010 96 ms 0011 128 ms 0100 160 ms 0101 192 ms 0110 224 ms 0111 256 ms 1000 288 ms 1001 320 ms 1010 352 ms 1011 384 ms 1100 416 ms 1101 448 ms 1110 480 ms 1111 512 ms open_coil[1:0] 00 2.56 ms defines the open coil detection time ? out. if an open coil is detected for a time longer than opentimeout[1:0], an open coil (open_x and/or open_y) will be reported. note: short circuit could trigger open coil detection. p23 01 0.32 ms 10 20.48 ms 11 163.84 ms remark: bit 0 of watchdog register should always be ?0? (zero)!
amis ? 30421 http://onsemi.com 31 control register 0 (cr0) control register 0 is located at address 0x01 and is used to set the maximum coil current and stepping mode. it?s also used to set the ?coil current zero crossing? duration. table 11. control register 0 control register 0 (cr0) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x01 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 data sm[2:0] min_sla_time[1:0] cur[2:0] table 12. control register 0 parameters parameter value value description info sm[2:0] 000 64 th defines the 8 stepping modes for the pwm regulator. p19 001 32 nd 010 16 th 011 8 th 100 4 th 101 half step compensated 110 half step uncompensated 111 full step min_sla_time[1:0] 00 40  s defines the minimum ?coil current zero crossing? duration. remark: when nxt frequency gets above pwm frequency (f pwm ), min_sla_time could be 40us longer. p20 01 120  s 10 200  s 11 360  s cur[2:0] 000 100 mv defines the maximum voltage over the coil current sense resistor which defines the maximum coil current. the maximum coil current is calculated as next: i coil = cur[2:0] / r sense p20 001 135 mv 010 200 mv 011 270 mv 100 335 mv 101 400 mv 110 500 mv 111 600 mv control register 1 (cr1) control register 1 is located at address 0x02 and can used to set the direction, nxt ? pin polarity, output configuration of wdb ? , errb ? and do ? pin and to enable pwm jitter. it can also be used to set an additional delay between switching off and on mosfet?s of one half h ? bridge (to prevent a short circuit). table 13. control register 1 control register 1 (cr1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x02 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 1 0 0 0 1 data dirctrl nxtp ? io_ot ? pwmj no_cross[1:0]
amis ? 30421 http://onsemi.com 32 table 14. control register 1 parameters parameter value value description info dirctrl 0 cw defines the direction of rotation. remark: cw and ccw is relative. direction of rotation will be defined by the status of the dir ? pin and connection of the stepper motor! p19 1 ccw nxtp 0 positive edge defines the active edge on the nxt ? pin. p19 1 negative edge io_ot 0 push pull defines the output type of wdb ? , errb ? and do ? pin p24 1 open drain pwmj 0 disabled enables or disables pwm jitter p15 1 enabled no_cross[1:0] 00 0 ns defines the time between switching off one mosfet and switching on the other mosfet of the same half h ? bridge (= t nocross ). p13 01 250 ns 10 500 ns 11 1000 ns remark: bit 3 and bit 5 of control register 1 should always be ?0? (zero)! control register 2 (cr2) control register 2 is located at address 0x03 and can be used to enable the motor driver and to put the motor driver in sleep mode. it also has some parameters that can be used to set the sla. table 15. control register 2 control register 2 (cr2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x03 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 data moten slp ? slat slag[2:0] sla_offs table 16. control register 2 parameters parameter value value description info moten 0 disabled enables the pwm regulator. remark: the regulator is automatically disabled if one of the bits in status register 1 or 2 is set. p19 1 enabled slp 0 normal mode enables the sleep mode (power down mode) p22 1 sleep mode slat 0 not transparent defines the type of sla sampling. p20 1 transparent slag[2:0] 000 1 defines the motor terminal voltage division factor for the sla ? pin. p20 001 0.5 010 0.25 011 0.125 100 0.0625 101 0.0625 110 0.0625 111 0.0625
amis ? 30421 http://onsemi.com 33 table 16. control register 2 parameters parameter info description value value sla_offs 0 no additional offset to enable an additional offset on the sla ? pin of 0.6v. p20 1 additional offset of 0.6 v remark: bit 5 of control register 2 should always be ?0? (zero)! status register 0 (sr0) status register 0 is located at address 0x04 and can only be read. status register 0 is a non ? latched register meaning that the value of the register can change without the need of reading out the register. the register can be used to retrieve the temperature range or to verify a watchdog event. notice that bit 7 is the parity bit (see read operation p26). table 17. status register 0 status register 0 (sr0) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x04 access r r r r r r r r reset 0 0 0 0 0 1 0 0 data par tr[1:0] wd ? ? ? ? table 18. status register 0 parameters parameter value value description info tr[1:0] 00 ? 40 c to 15 c motor driver thermal range. remark: tr[1:0] = 11 and tsd = 0 => thermal warning tr[1:0] = 11 and tsd = 1 => thermal shutdown tsd is located in status register 2 p23 01 15 c to 72 c 10 73 c to 150 c 11 tsd = 0: 150 c to 170 c tsd = 1: >170 c wd 0 no watchdog event if wden = 1 and watchdog not acknowledged before the watchdog time ? out (wdt[3:0]), wdb ? pin will be pulled low for 100ms to reset an external microcontroller and wd bit will be set to ?1? to indicate this event. the external mi- crocontroller can use this bit to verify a cold (wd = 0) or warm boot (wd = 1). p24 1 watchdog event occurred status register 1 (sr1) status register 1 is located at address 0x05 and can only be read. status register 1 is a latched register. if an error occurs the bit will be set and can only be cleared by reading out this bit 1 . the register is used to report an overcurrent or open coil in the x ? coil, or to report a charge pump failure. notice that bit 7 is the parity bit (see read operation p26). table 19. status register 1 status register 1 (sr1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x05 access r r r r r r r r reset 0 0 0 0 0 0 0 0 data par ovcxpt ovcxpb ovcxnt ovcxnb cpfail open_x ? 1. in sleep mode the register can be read out but will not be cleared!
amis ? 30421 http://onsemi.com 34 table 20. status register 1 parameters parameter value value description info ovcxpt 0 no overcurrent overcurrent detection in top transistor xp ? terminal p23 1 overcurrent ovcxpb 0 no overcurrent overcurrent detection in bottom transistor xp ? terminal p23 1 overcurrent ovcxnt 0 no overcurrent overcurrent detection in top transistor xn ? terminal p23 1 overcurrent ovcxnb 0 no overcurrent overcurrent detection in bottom transistor xn ? terminal p23 1 overcurrent cpfail 0 no charge pump failure charge pump failure detection p23 1 charge pump failure open_x 0 no open coil detected open coil detection for x ? coil note: a short circuit could trigger an open coil p23 1 open coil detected status register 2 (sr2) status register 2 is located at address 0x06 and can only be read. status register 2 is a latched register. if an error occurs the bit will be set and can only be cleared by reading out this bit 2 . the register is used to report an overcurrent or open coil in the y ? coil, or to report a thermal shutdown. notice that bit 7 is the parity bit (see read operation p26). table 21. status register 2 status register 2 (sr2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x06 access r r r r r r r r reset 0 0 0 0 0 0 0 0 data par ovcypt ovcypb ovcynt ovcynb tsd open_y ? table 22. status register 2 parameters parameter value value description info ovcypt 0 no overcurrent overcurrent detection in top transistor yp ? terminal p23 1 overcurrent ovcypb 0 no overcurrent overcurrent detection in bottom transistor yp ? terminal p23 1 overcurrent ovcynt 0 no overcurrent overcurrent detection in top transistor yn ? terminal p23 1 overcurrent ovcynb 0 no overcurrent overcurrent detection in bottom transistor yn ? terminal p23 1 overcurrent tsd 0 no thermal shutdown thermal shutdown detection p23 1 thermal shutdown open_y 0 no open coil detected open coil detection for x ? coil note: a short circuit could trigger an open coil p23 1 open coil detected 2. in sleep mode the register can be read out but will not be cleared!
amis ? 30421 http://onsemi.com 35 status register 3 (sr3) status register 3 is located at address 0x07 and can only be read. status register 3 contains the microstepping position and can be used to retrieve the position in the translator table (see table 7). it is a non ? latched register meaning that the microstepping position can be updated by the motor driver at any moment. status register 3 does not contain a parity bit. table 23. status register 3 status register 3 (sr3) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x07 access r r r r r r r r reset 0 0 0 0 0 0 0 0 data msp[7:0] table 24. status register 3 parameters parameter value value description info msp[7:0] xxxx xxxx microstepping position indicates the position within the translator table p19 predriver register 0 (pdrv0) predriver register 0 is located at address 0x09 and can be used to set the current source for the gate charge of the external top mosfet?s during t 1 (see figure 11). table 25. predriver register 0 predriver register 0 (pdrv0) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x09 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 1 0 0 1 1 data top_ion1[6:3] ? top_ion1[2:0] table 26. predriver register 0 parameters parameter value value description info top_ion1[6:3] xxxx current source value defines the current source for the external top mosfet?s during t 1 . current source can be calculated as next: 1 ma + (pdrv0[7:4] x 2 ma) + 0.25 ma + (pdrv0[2:0] x 0.25 ma) p13 top_ion1[2:0] xxx predriver register 1 (pdrv1) predriver register 1 is located at address 0x0a and can be used to set the current source for the gate charge of the external top mosfet?s during t 2 (see figure 11). table 27. predriver register 1 predriver register 1 (pdrv1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0a access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 1 1 data top_ion2[6:3] ? top_ion2[2:0]
amis ? 30421 http://onsemi.com 36 table 28. predriver register 1 parameters parameter value value description info top_ion2[6:3] xxxx current source value defines the current source for the external top mosfet?s during t 2 . current source can be calculated as next: 1 ma + (pdrv1[7:4] x 2 ma) + 0.25 ma + (pdrv1[2:0] x 0.25 ma) p13 top_ion2[2:0] xxx predriver register 2 (pdrv2) predriver register 2 is located at address 0x0b and can be used to set the current source for the gate charge of the external bottom mosfet?s during t 1 (see figure 11). table 29. predriver register 2 predriver register 2 (pdrv2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0b access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 1 0 0 1 1 data bot_ion1[6:3] ? bot_ion1[2:0] table 30. predriver register 2 parameters parameter value value description info bot_ion1[6:3] xxxx current source value defines the current source for the external bottom mosfet?s during t 1 . current source can be calculated as next: 1 ma + (pdrv2[7:4] x 2 ma) + 0.25 ma + (pdrv2[2:0] x 0.25 ma) p13 bot_ion1[2:0] xxx predriver register 3 (pdrv3) predriver register 3 is located at address 0x0c and can be used to set the current source for the gate charge of the external bottom mosfet?s during t 2 (see figure 11). table 31. predriver register 3 predriver register 3 (pdrv3) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0c access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 1 1 data bot_ion2[6:3] ? bot_ion2[2:0] table 32. predriver register 3 parameters parameter value value description info bot_ion2[6:3] xxxx current source value defines the current source for the external bottom mosfet?s dur- ing t 2 . current source can be calculated as next: 1 ma + (pdrv3[7:4] x 2 ma) + 0.25 ma + (pdrv3[2:0] x 0.25 ma) p13 bot_ion2[2:0] xxx
amis ? 30421 http://onsemi.com 37 predriver register 4 (pdrv4) predriver register 4 is located at address 0x0d and can be used to set the current source for the gate discharge of the external mosfet?s (see figure 11). table 33. predriver register 4 predriver register 4 (pdrv4) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0d access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 0 1 0 0 data top_ioff[3:0] bot_ioff[3:0] table 34. predriver register 4 parameters parameter value value description info top_ioff[3:0] xxxx current source value defines the current source for the external top mosfet?s during t off . current source can be calculated as next: 10.5 ma + (pdrv4[7:4] x 7 ma) p13 bot_ioff[3 :0] xxxx current source value defines the current source for the external bottom mosfet?s dur- ing t off . current source can be calculated as next: 10.5 ma + (pdrv4[3:0] x 7 ma) p13 predriver register 5 (pdrv5) predriver register 5 is located at address 0x0e and can be used to set t 2 (see figure 11). table 35. predriver register 5 predriver register 5 (pdrv5) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0e access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 0 1 0 0 data ? top_t2[2:0] ? bot_t2[2:0] table 36. predriver register 5 parameters parameter value value description info top_t2[2:0] 000 1.25  s defines the switch on duration t 2 for the external top mosfet?s. p13 001 1.75  s 010 2.25  s 011 2.75  s 100 3.25  s 101 3.75  s 110 4.25  s 111 4.75  s
amis ? 30421 http://onsemi.com 38 table 36. predriver register 5 parameters parameter info description value value bot_t2[2 :0] 000 1.25  s defines the switch on duration t 2 for the external bottom mosfet?s. p13 001 1.75  s 010 2.25  s 011 2.75  s 100 3.25  s 101 3.75  s 110 4.25  s 111 4.75  s predriver register 6 (pdrv6) predriver register 6 is located at address 0x0f and can be used to set t off (see figure 11). table 37. predriver register 6 predriver register 6 (pdrv6) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0f access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 1 0 0 0 1 0 0 data ? top_toff[2:0] ? bot_toff[2:0] table 38. predriver register 6 parameters parameter value value description info top_toff[2:0] 000 1.25  s defines the switch off duration (t off ) for the external top mosfet?s. p13 001 1.75  s 010 2.25  s 011 2.75  s 100 3.25  s 101 3.75  s 110 4.25  s 111 4.75  s bot_toff[2 :0] 000 1.25  s defines the switch off duration (t off ) for the external bottom mosfet?s. p13 001 1.75  s 010 2.25  s 011 2.75  s 100 3.25  s 101 3.75  s 110 4.25  s 111 4.75  s
amis ? 30421 http://onsemi.com 39 predriver register 7 (pdrv7) predriver register 7 is located at address 0x10 and can be used to set t 1 (see figure 11). table 39. predriver register 7 predriver register 7 (pdrv7) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x10 access r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 1 0 data ? top_t1[2:0] ? bot_t1[2:0] table 40. predriver register 7 parameters parameter value value description info top_t1[2:0] 000 375 ns defines the switch on duration t 1 for the external top mosfet?s. p13 001 500 ns 010 625 ns 011 750 ns 100 875 ns 101 1000 ns 110 1125 ns 111 1250 ns bot_t1[2 :0] 000 375 ns defines the switch on duration t 1 for the external bottom mosfet?s. p13 001 500 ns 010 625 ns 011 750 ns 100 875 ns 101 1000 ns 110 1125 ns 111 1250 ns
amis ? 30421 http://onsemi.com 40 package thermal characteristics the amis ? 30421 is available in a nqfp44 package. for cooling optimizations, the nqfp has an exposed thermal pad which has to be soldered to the pcb ground plane. the ground plane needs thermal vias to conduct the heat to the bottom layer. figure 35 gives an example of good heat transfer. the exposed thermal pad is soldered directly on the top ground layer (left picture of figure 35). it?s advised to make the top ground layer as large as possible (see arrows figure 35). to improve the heat transfer even more, the exposed thermal pad is connected to a bottom ground layer by using thermal vias (see right picture of figure 35). it?s advised to make this bottom ground layer as large as possible and with as less as possible interruptions. for precise thermal cooling calculations the major thermal resistances of the device are given (table 4). the thermal media to which the power of the devices has to be given are: ? static environmental air (via the case) ? pcb board copper area (via the exposed pad) the major thermal resistances of the device are the rth from the junction to the ambient (rth ja ) and the overall rth from the junction to exposed pad (rth jp ). in table 4 one can find the values for the rth ja and rth jp , simulated according to jesd ? 51. the rth ja for 2s2p is simulated conform jedec jesd ? 51 as follows: ? a 4 ? layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used ? board thickness is 1,46mm (fr4 pcb material) ? the 2 signal layers: 70 um thick copper with an area of 5500 mm 2 copper and 20% conductivity ? the 2 power internal planes: 36  m thick copper with an area of 5500 mm 2 copper and 90% conductivity the rth ja for 1s0p is simulated conform to jedec jesd ? 51 as follows: ? a 1 ? layer printed circuit board with only 1 layer ? board thickness is 1.46 mm (fr4 pcb material) ? the layer has a thickness of 70  m copper with an area of 5500 mm 2 copper and 20% conductivity 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 figure 35. pcb ground plane layout condition (left picture displays the top ground layer, right picture displays the bottom ground layer) ordering information part no. peak current temperature range package shipping ? AMIS30421C4211G na ? 40 c to +170 c nqfp ? 44 (7 x 7 mm) (pb ? free) units / tube amis30421c4211rg tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
amis ? 30421 http://onsemi.com 41 package dimensions qfn44 7x7, 0.5p case 485by issue o ???? ???? ???? ???? note 3 seating plane k 0.15 c (a3) a a1 d2 b 1 12 23 44 34 e2 44x 11 33 l 44x bottom view top view side view 0.15 c d a b e pin 1 reference 0.08 c 0.05 c e c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to the plated terminal and is measured abetween 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 0.90 a1 ??? 0.05 a3 0.20 ref b 0.20 0.30 d 7.00 bsc d2 4.60 4.80 e 7.00 bsc e2 4.60 4.80 e 0.50 bsc k 0.20 ??? l 0.45 0.65 note 4 dimensions: millimeters 0.50 4.90 0.30 44x 7.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 detail a 2x 2x 0.82 44x l1 detail a l alternate constructions l ??? 0.15 a 0.10 b c 0.05 c m m a m 0.10 b c a m 0.10 b c pitch detail b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 amis ? 30421/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative


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